Veröffentlichungen
2017 |
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C. Gemmel, J. Hensen, S. Kajari-Schröder, and R. Brendel IEEE Journal of Photovoltaics 7 (2), 430-436, (2017), ISSN: 2156-3381. Abstract | Links | BibTeX | Schlagwörter: charge carrier lifetime, Epitaxial growth, Epitaxy, Gettering, minority carrier lifetime, porous silicon (PSI), silicon, Substrates, Surface treatment, Temperature measurement @article{Gemmel2017,
title = {4.5 ms Effective Carrier Lifetime in Kerfless Epitaxial Silicon Wafers From the Porous Silicon Process}, author = {C Gemmel and J Hensen and S Kajari-Schröder and R Brendel}, doi = {10.1109/JPHOTOV.2016.2642640}, issn = {2156-3381}, year = {2017}, date = {2017-03-01}, journal = {IEEE Journal of Photovoltaics}, volume = {7}, number = {2}, pages = {430-436}, abstract = {Kerfless silicon wafers epitaxially grown on porous silicon (PSI) and subsequently detached from the growth substrate are a promising candidate for reducing the cost of the silicon wafer, which is particularly important for silicon photovoltaics. However, the carrier lifetime of these epitaxial wafers has to be at least as high as that of today's standard Czochralski (Cz)-grown wafers in order to become competitive. Here, we compare the measured lifetimes of n-type epitaxial silicon wafers that grow on PSI and epitaxial silicon wafers that grow on nonporous surfaces of epi-ready wafers. The latter are subsequently ground to have free-standing epitaxial wafers. Gettering improves the carrier lifetime of the ground wafers up to 4.2 ms. In contrast, PSI wafers show regions with effective lifetimes of 4.5 ms, even without gettering. This lifetime value is a factor of four larger than lifetimes of Cz wafers which are typically employed in today's PERC solar cells. We model the lifetime measurements with three Shockley-Read-Hall (SRH) defects: two defects that exist in the PSI and in the epi-ready wafer and a third defect that is only present in the epi-ready wafer.}, keywords = {charge carrier lifetime, Epitaxial growth, Epitaxy, Gettering, minority carrier lifetime, porous silicon (PSI), silicon, Substrates, Surface treatment, Temperature measurement}, pubstate = {published}, tppubtype = {article} } Kerfless silicon wafers epitaxially grown on porous silicon (PSI) and subsequently detached from the growth substrate are a promising candidate for reducing the cost of the silicon wafer, which is particularly important for silicon photovoltaics. However, the carrier lifetime of these epitaxial wafers has to be at least as high as that of today's standard Czochralski (Cz)-grown wafers in order to become competitive. Here, we compare the measured lifetimes of n-type epitaxial silicon wafers that grow on PSI and epitaxial silicon wafers that grow on nonporous surfaces of epi-ready wafers. The latter are subsequently ground to have free-standing epitaxial wafers. Gettering improves the carrier lifetime of the ground wafers up to 4.2 ms. In contrast, PSI wafers show regions with effective lifetimes of 4.5 ms, even without gettering. This lifetime value is a factor of four larger than lifetimes of Cz wafers which are typically employed in today's PERC solar cells. We model the lifetime measurements with three Shockley-Read-Hall (SRH) defects: two defects that exist in the PSI and in the epi-ready wafer and a third defect that is only present in the epi-ready wafer.
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2016 |
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J. Krügener, Y. Larionova, B. Wolpensinger, D. Tetzlaff, S. Reiter, M. Turcu, R. Peibst, J. -D. Kähler, and T. Wietler Dopant diffusion from p+-poly-Si into c-Si during thermal annealing Inproceedings IEEE (Hrsg.): 2016 IEEE 43rd Photovoltaic Specialists Conference (PVSC), 2451-2454, Portland, OR, USA, (2016), ISBN: 978-1-5090-2725-5. Abstract | Links | BibTeX | Schlagwörter: Annealing, boron, diffusion, junction formation, Junctions, low pressure chemical vapor deposition, passivating contacts, Resistance, Scanning electron microscopy, silicon, Substrates, Temperature measurement @inproceedings{Krügener2016b,
title = {Dopant diffusion from p+-poly-Si into c-Si during thermal annealing}, author = {J Krügener and Y Larionova and B Wolpensinger and D Tetzlaff and S Reiter and M Turcu and R Peibst and J -D Kähler and T Wietler}, editor = {IEEE}, doi = {10.1109/PVSC.2016.7750083}, isbn = {978-1-5090-2725-5}, year = {2016}, date = {2016-06-01}, booktitle = {2016 IEEE 43rd Photovoltaic Specialists Conference (PVSC)}, journal = {Proceedings of the 43rd IEEE Photovoltaic Specialists Conference}, pages = {2451-2454}, address = {Portland, OR, USA}, abstract = {Passivating junctions, like hole-collecting p-polycrystalline silicon/SiOx/crystalline silicon junctions, need a thermal activation to activate their excellent passivation and contact properties. Here, the diffusion of boron from the highly doped poly-Si layer into the Si is often considered to compromise the passivation quality. In contrast we show that at least a slight diffusion of boron into the crystalline silicon is present for optimized annealing conditions. We achieve low emitter saturation current densities of 11 fA/cm2 for in situ p+ doped polysilicon deposited by low pressure chemical vapor deposition. Furthermore, we show that the polysilicon layer and the in-diffused region within the substrate are electrically connected.}, keywords = {Annealing, boron, diffusion, junction formation, Junctions, low pressure chemical vapor deposition, passivating contacts, Resistance, Scanning electron microscopy, silicon, Substrates, Temperature measurement}, pubstate = {published}, tppubtype = {inproceedings} } Passivating junctions, like hole-collecting p-polycrystalline silicon/SiOx/crystalline silicon junctions, need a thermal activation to activate their excellent passivation and contact properties. Here, the diffusion of boron from the highly doped poly-Si layer into the Si is often considered to compromise the passivation quality. In contrast we show that at least a slight diffusion of boron into the crystalline silicon is present for optimized annealing conditions. We achieve low emitter saturation current densities of 11 fA/cm2 for in situ p+ doped polysilicon deposited by low pressure chemical vapor deposition. Furthermore, we show that the polysilicon layer and the in-diffused region within the substrate are electrically connected.
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V. Steckenreiter, J. Hensen, A. Knorr, S. Kajari-Schröder, and R. Brendel Reuse of substrate wafers for the porous silicon layer transfer Artikel IEEE Journal of Photovoltaics 6 (3), 783-790, (2016). Abstract | Links | BibTeX | Schlagwörter: Carrier lifetime, charge carrier lifetime, Contamination, Epitaxial growth, epitaxial layer, Epitaxial layers, layer transfer, Photovoltaic systems, porous silicon (PSI) process, silicon, substrate reuse, Substrates @article{Steckenreiter2016b,
title = {Reuse of substrate wafers for the porous silicon layer transfer}, author = {V Steckenreiter and J Hensen and A Knorr and S Kajari-Schröder and R Brendel}, doi = {10.1109/JPHOTOV.2016.2545406}, year = {2016}, date = {2016-05-01}, journal = {IEEE Journal of Photovoltaics}, volume = {6}, number = {3}, pages = {783-790}, abstract = {The reuse of the silicon substrate is a key component in the kerfless-porous-silicon-based wafering process. Starting with a boron-doped p+-type substrate, a porous double layer is created, reorganized in a hydrogen bake, and then serves as a substrate for silicon homoepitaxy. After lift-off, the silicon substrate is wet chemically reconditioned and reporosified to serve again as a substrate for epitaxial layer deposition. We reduce the substrate consumption per cycle to 5 ± 0.3 μm/side and demonstrate 14 uses on a 6-in wafer. We investigate the impact of the reuse sequence on the epitaxial layer quality by carrier lifetime measurements. Starting with the third reuse, a pattern becomes visible in lifetime mappings. We observe a degradation of the minority carrier lifetime from 15 to 7 μs after 13 reuses.}, keywords = {Carrier lifetime, charge carrier lifetime, Contamination, Epitaxial growth, epitaxial layer, Epitaxial layers, layer transfer, Photovoltaic systems, porous silicon (PSI) process, silicon, substrate reuse, Substrates}, pubstate = {published}, tppubtype = {article} } The reuse of the silicon substrate is a key component in the kerfless-porous-silicon-based wafering process. Starting with a boron-doped p+-type substrate, a porous double layer is created, reorganized in a hydrogen bake, and then serves as a substrate for silicon homoepitaxy. After lift-off, the silicon substrate is wet chemically reconditioned and reporosified to serve again as a substrate for epitaxial layer deposition. We reduce the substrate consumption per cycle to 5 ± 0.3 μm/side and demonstrate 14 uses on a 6-in wafer. We investigate the impact of the reuse sequence on the epitaxial layer quality by carrier lifetime measurements. Starting with the third reuse, a pattern becomes visible in lifetime mappings. We observe a degradation of the minority carrier lifetime from 15 to 7 μs after 13 reuses.
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2014 |
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J. H. Petermann, H. Schulte-Huxel, V. Steckenreiter, S. Kajari-Schroder, and R. Brendel Principle of module-level processing demonstrated at single a-Si:H/c-Si heterojunction solar cells Artikel IEEE Journal of Photovoltaics 4 (4), 1018-1024, (2014). Links | BibTeX | Schlagwörter: Contact recombination velocity, Glass, heterojunction, Hybrid silicon, Indium tin oxide, laser-fired and bonding contacts (LFBCs), module-level processing, passivation, Photovoltaic cells, silicon, Silicon compounds, silicone, Substrates @article{Petermann2014,
title = {Principle of module-level processing demonstrated at single a-Si:H/c-Si heterojunction solar cells}, author = {J H Petermann and H Schulte-Huxel and V Steckenreiter and S Kajari-Schroder and R Brendel}, doi = {10.1109/JPHOTOV.2014.2314576}, year = {2014}, date = {2014-07-01}, journal = {IEEE Journal of Photovoltaics}, volume = {4}, number = {4}, pages = {1018-1024}, keywords = {Contact recombination velocity, Glass, heterojunction, Hybrid silicon, Indium tin oxide, laser-fired and bonding contacts (LFBCs), module-level processing, passivation, Photovoltaic cells, silicon, Silicon compounds, silicone, Substrates}, pubstate = {published}, tppubtype = {article} } |
2012 |
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H. Schulte-Huxel, Bock.. R. S. Blankemeyer, A. Merkle, and R. Brendel IEEE Journal of Photovoltaics 2 (1), 16-21, (2012). Links | BibTeX | Schlagwörter: Al-metallization, Back-contact solar cells, Glass, Laser microwelding, Lasers, Lead-free, Measurement by laser beam, module-level interconnection, Photovoltaic cells, photovoltaic module, Stress, Substrates, Welding @article{Schulte-Huxel2012b,
title = {Aluminum-based mechanical and electrical laser interconnection process for module integration of silicon solar cells}, author = {H Schulte-Huxel and Bock. R S Blankemeyer and A Merkle and R Brendel}, doi = {10.1109/JPHOTOV.2011.2177072}, year = {2012}, date = {2012-01-01}, journal = {IEEE Journal of Photovoltaics}, volume = {2}, number = {1}, pages = {16-21}, keywords = {Al-metallization, Back-contact solar cells, Glass, Laser microwelding, Lasers, Lead-free, Measurement by laser beam, module-level interconnection, Photovoltaic cells, photovoltaic module, Stress, Substrates, Welding}, pubstate = {published}, tppubtype = {article} } |
2010 |
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Y. Larionova, N. P. Harder, and R. Brendel Effect of SiO2 thicknesses in thermal-SiO2/PECVD-SiN stacks on surface passivation of n-type Cz silicon substrates Inproceedings IEEE (Hrsg.): 2010 35th IEEE Photovoltaic Specialists Conference, 001207-001209, Honolulu, HI, USA, (2010), ISSN: 0160-8371. Links | BibTeX | Schlagwörter: Annealing, Degradation, passivation, silicon, Silicon compounds, Substrates @inproceedings{Larionova2010,
title = {Effect of SiO2 thicknesses in thermal-SiO2/PECVD-SiN stacks on surface passivation of n-type Cz silicon substrates}, author = {Y Larionova and N P Harder and R Brendel}, editor = {IEEE}, doi = {10.1109/PVSC.2010.5614072}, issn = {0160-8371}, year = {2010}, date = {2010-06-01}, booktitle = {2010 35th IEEE Photovoltaic Specialists Conference}, pages = {001207-001209}, address = {Honolulu, HI, USA}, keywords = {Annealing, Degradation, passivation, silicon, Silicon compounds, Substrates}, pubstate = {published}, tppubtype = {inproceedings} } |
2009 |
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F. Haase, R. Horbelt, B. Terheiden, H. Plagwitz, and R. Brendel Back contact monocrystalline thin-film silicon solar cells from the porous silicon process Inproceedings IEEE (Hrsg.): 2009 34th IEEE Photovoltaic Specialists Conference (PVSC), 000244-000246, Philadelphia, PA, USA, (2009), ISSN: 0160-8371. Links | BibTeX | Schlagwörter: Etching, Lithography, metallization, Optical pulses, passivation, Photovoltaic cells, Semiconductor thin films, Silicon compounds, Substrates, Surface emitting lasers @inproceedings{Haase2009,
title = {Back contact monocrystalline thin-film silicon solar cells from the porous silicon process}, author = {F Haase and R Horbelt and B Terheiden and H Plagwitz and R Brendel}, editor = {IEEE}, doi = {10.1109/PVSC.2009.5411686}, issn = {0160-8371}, year = {2009}, date = {2009-06-01}, booktitle = {2009 34th IEEE Photovoltaic Specialists Conference (PVSC)}, pages = {000244-000246}, address = {Philadelphia, PA, USA}, keywords = {Etching, Lithography, metallization, Optical pulses, passivation, Photovoltaic cells, Semiconductor thin films, Silicon compounds, Substrates, Surface emitting lasers}, pubstate = {published}, tppubtype = {inproceedings} } |
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E. G. Rojas, C. Hampe, H. Plagwitz, and R. Brendel Formation of mesoporous gallium arsenide for lift-off processes by electrochemical etching Inproceedings IEEE (Hrsg.): 2009 34th IEEE Photovoltaic Specialists Conference (PVSC), 001086-001089, Philadelphia, PA, USA, (2009), ISSN: 0160-8371. Links | BibTeX | Schlagwörter: Conductive films, Conductivity, Epitaxial growth, Etching, Gallium arsenide, Glass, Mesoporous materials, Molecular beam epitaxial growth, Substrates, X-ray scattering @inproceedings{Rojas2009b,
title = {Formation of mesoporous gallium arsenide for lift-off processes by electrochemical etching}, author = {E G Rojas and C Hampe and H Plagwitz and R Brendel}, editor = {IEEE}, doi = {10.1109/PVSC.2009.5411208}, issn = {0160-8371}, year = {2009}, date = {2009-06-01}, booktitle = {2009 34th IEEE Photovoltaic Specialists Conference (PVSC)}, pages = {001086-001089}, address = {Philadelphia, PA, USA}, keywords = {Conductive films, Conductivity, Epitaxial growth, Etching, Gallium arsenide, Glass, Mesoporous materials, Molecular beam epitaxial growth, Substrates, X-ray scattering}, pubstate = {published}, tppubtype = {inproceedings} } |
2008 |
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B. Hoex, J. Schmidt, M. C. M. van de Sanden, and W. M. M. Kessels Crystalline silicon surface passivation by the negative-charge-dielectric Al2O3 Inproceedings IEEE (Hrsg.): 2008 33rd IEEE Photovoltaic Specialists Conference, 1-4, San Diego, CA, USA, (2008), ISSN: 0160-8371. Links | BibTeX | Schlagwörter: atomic layer deposition, Conductivity, Crystallization, Doping, passivation, Photovoltaic cells, Plasma temperature, silicon, Substrates, Velocity measurement @inproceedings{Hoex2008b,
title = {Crystalline silicon surface passivation by the negative-charge-dielectric Al2O3}, author = {B Hoex and J Schmidt and M C M van de Sanden and W M M Kessels}, editor = {IEEE}, doi = {10.1109/PVSC.2008.4922635}, issn = {0160-8371}, year = {2008}, date = {2008-05-01}, booktitle = {2008 33rd IEEE Photovoltaic Specialists Conference}, pages = {1-4}, address = {San Diego, CA, USA}, keywords = {atomic layer deposition, Conductivity, Crystallization, Doping, passivation, Photovoltaic cells, Plasma temperature, silicon, Substrates, Velocity measurement}, pubstate = {published}, tppubtype = {inproceedings} } |